1. Field of the Invention
The present invention relates to a technique for attaining high breakdown voltage in a level shift circuit without increasing the thickness of the gate oxides of the MOS transistors used therein, which circuit transmits a signal from its low supply voltage side to its high supply voltage side. More particularly, the invention relates to a technique suitably applicable to level shift circuits and semiconductor devices for use in, e.g., switching regulators and others.
2. Description of the Related Art
The level shift circuits, which have heretofore been developed, have such a configuration as shown in FIG. 13.
FIG. 13 shows one known level shift circuit that is cited in JP-A-2004-72829 (Page 11 and FIG. 6).
The known level shift circuit will be described with reference to FIG. 13.
In FIG. 13, numerals 76, 81 each designate an inverter; numerals 79, 80 designate a PMOS transistor (hereinafter referred to as a “PMOS”); numerals 77, 78 designate an NMOS transistor (hereinafter referred to as an “NOMS”); Vdd1 designates a first high potential side power supply; Vdd2 designates a second high potential side power supply; Vss1 designates a low potential side power supply; VIN designates a signal input terminal; and VOUT designates a signal output terminal.
In the known level shift circuit, the signal input terminal VIN is connected to the gate of the NMOS (78) and to the input terminal of the inverter (76) whose earth terminal is connected to the Vss1 and whose power supply terminal is connected to the Vdd1. The output terminal of the inverter (76) is connected to the gate of the NMOS (77). The PMOSs (79) and (80), whose sources are connected to the Vdd2, are interconnected, with the gates of the PMOS (79), (80) being connected to the drains of the PMOSs (80), (79) respectively. The drain of the PMOS (79) is connected to the Vss1 through the NMOS (77), and the drain of the PMOS (80) is connected to the Vss1 through the NMOS (78). The drain of the PMOS (80) is also connected to the input terminal of the inverter (81) whose earth terminal is connected to the Vss1 and whose power supply terminal is connected to the Vdd2. The output of the inverter (81) is connected to the signal output terminal VOUT.
This circuit is for level shifting an input signal VIN generated by a supply voltage [Vdd1−Vss1(GND)] to output an output signal VOUT whose amplitude differs from the input signal VIN, using a supply voltage [Vdd2−Vss1] that differs from the supply voltage [Vdd1−Vss1].
The level shift circuit shown in FIG. 13 is operable when the potential of the Vdd2 is lower than that of the Vdd1. However, if the Vdd2 becomes higher, a high potential difference [Vdd2−Vss1] is applied as the gate to source voltage VGS of the PMOS (79) and the PMOS (80) and therefore there is a need to increase the breakdown voltages (withstand voltages) of the elements. Generally, element breakdown caused by application of a high voltage across a gate and a source is avoided by increasing breakdown voltage by thickening the gate oxide of the element. However, thickening of the gate oxide is accompanied by an increase in the size of the element, which leads to not only an increase in the cost of the IC but also the problem that the threshold voltage Vth (that is, the operating voltage) of the MOS transistor increases and the inversion speed of the MOS transistor decreases.
To overcome the problem presented by the circuit shown in FIG. 13, a configuration such as shown in FIG. 12 is proposed by JP-A-2004-72829. FIG. 12 shows a known level shift circuit disclosed in JP-A-2004-72829 (Page 10, FIG. 1).
This known level shift circuit will be described with reference to FIG. 12.
Referring to FIG. 12, numerals 59, 73 each designate an inverter; numerals 68, 69 designate a PMOS; numerals 60, 61, 63, 64, 65, 71, 72 designate an NMOS; numerals 66. 67 designate a drain high breakdown voltage NMOS transistor (hereinafter referred to as a “drain high breakdown voltage NMOS”); numerals 62, 70 designate a resistor, numeral 74 designates a first constant current circuit; numeral 75 designates a second constant current circuit; Vdd1 designates a first high potential side power supply; Vdd2 designates a second high potential side power supply; Vss1 designates a first low potential side power supply; Vss2 designates a second low potential side power supply; VIN designates a signal input terminal and VOUT designates a signal output terminal.
The drain high breakdown voltage NMOSs are NMOS transistors in which the drain has high breakdown voltage and therefore element breakdown can be avoided even if a high voltage is applied across the gate and drain or across the source and drain.
This circuit is intended to level shift the input signal VIN generated by a supply voltage [Vdd1−Vss1] to output the output signal VOUT, using a supply voltage [Vdd2−Vss2] that is higher in potential than the supply voltage [Vdd1−Vss1]. Herein, the output signal VOUT has higher central potential than that of the input signal VIN.
According to JP-A-2004-72829, the operating condition for the circuit shown in FIG. 12 is as follows.
The following description is written in Page 4, Paragraph No. 0009.
“The above supply voltage [Vdd2−Vss2] is substantially the same in potential difference as the supply voltage [Vdd1−Vss1 (GND)] (e.g., 10V-5V) of a logic system, but only the potential of [Vdd2−Vss2] is higher than that of [Vdd1−Vss1]”
The following description is written in Page 5, Paragraph No. 0016.
“the reference potential for the high potential side (lower supply voltage) Vss2”
According to this operating condition, the voltage of the Vdd1 (lower supply voltage) is the same as that of the Vss2 (reference potential for the high potential side). The supply voltage [Vdd2−Vss2] is substantially the same as the supply voltage [Vdd1−Vss 1] in potential difference but higher than the supply voltage [Vdd1−Vss1] only in potential. This indicates that the potential difference of the supply voltage [Vdd2−Vss1] needs to be substantially twice that of the supply voltage [Vdd1−Vss1]. The circuit shown in FIG. 12 operates on the condition that the potential of the Vdd2 is higher than that of the Vdd1.
The level shift circuit shown in FIG. 12 is comprised of:
a pair of input MOS transistors NMOS (60), NMOS (61) that receive, at their gates, an input signal VIN and its inversion signal respectively;
current mirror-connected load MOS transistors PMOS (68), PMOS (69) whose sources are connected to the Vdd2;
drain high breakdown voltage MOS transistors NMOS (66), NMOS (67) and current limitation MOS transistors NMOS (64), NMOS (65) for limiting the currents flowing in the NMOS (66), NMOS (67) respectively, the NMOS (66) being connected in series between the input MOS transistor NMOS (60) and the load MOS transistor PMOS (68) whereas the NMOS (67) is connected in series between the input MOS transistor NMOS (61) and the load MOS transistor PMOS (69);
a first constant current circuit (74) that determines the amount of electric current flowing in the current limitation MOS transistors NMOS (64), NMOS (65);
a current supply MOS transistor NMOS (71) that supplies electric current in order to prevent the drain potential of the drain high breakdown voltage MOS transistor NMOS (67) from excessively dropping;
a second constant current circuit (75) that determines the amount of electric current flowing in the NMOS (71); and
an inverter (73) that shapes the waveform of an output voltage to output the output voltage, the output voltage being generated at the drain of the load MOS transistor PMOS (69).
The sources of the NMOSs (60) and (61) are connected to the Vss1 and the input signal VIN is directly input into the gate of one of them. An inversion signal produced by inversion of the input signal VIN by the inverter (59) is input into the gate of the other NMOS, and the NMOSs (60), (61) are turned ON or OFF in accordance with the signal level of the input signal VIN.
The sources of the PMOSs (68), (69) are connected to the Vdd2, and the gate and drain of the PMOS (68) are connected together. The drain voltage of the PMOS (68) is applied to the gate of the PMOS (69).
The drains of the drain high breakdown voltage NMOSs (66), (67) are connected to the PMOS (68) side and the PMOS (69) side respectively. Their sources are connected to the NMOS (60) side and the NMOS (61) side respectively. The Vdd1 is connected to the gates of the NMOSs (66), (67) so as to apply voltage thereto. According to such NMOSs (66) and (67), even if high voltage is applied to their drains, the source potential is clamped to a clamp voltage (Vdd1−Vth) determined by the gate potential (Vdd1) and the threshold voltage Vth of the MOS transistors so that the high voltage is not applied to the elements NMOSs (64), (65), (60), (61) located on their source sides.
The NMOS (64) is connected in series between the NMOSs (60) and (66) whereas the NMOS (65) is connected in series between the NMOSs (61) and (67), and the NMOSs (64), (65) are current mirror-connected to the NMOS (63) that constitutes the first constant current circuit (74). When either the NMOS (60) or the NMOS (61) is in its ON state, the electric current flowing in its associated transistor NMOS (66) or NMOS (67) is limited to the amount of current determined by the first constant current circuit (74).
The first constant current circuit (74) is constituted by the NMOS (63) whose gate and drain are connected together and the resistor (62), the NMOS (63) and the resistor (62) being connected in series between the Vdd1 and the Vss1. The NMOS (71) is current mirror-connected to the NMOS (72) of the second constant current circuit (75) and feeds a current determined by the second constant current circuit (75) to an output node N11 when the potential of the output node 11 has dropped, so that the potential of the N11 is controlled to be prevented from becoming lower than the reference potential (lower supply voltage) Vss2 of the high potential side. As long as the potential of the N11 is prevented from becoming lower than the reference potential Vss2 by the current limitation with the NMOSs (64) and (65) or similar means, the NMOS (71) and the second constant current circuit (75) may be omitted. In the second constant current circuit (75), the resistor (70) and the NMOS (72) are connected in series between the Vdd2 and the Vss2. In the level shift circuit of the configuration described above, when the input signal VIN is at an H level, one (61) of the input NMOSs is turned ON so that current flows through the PMOS (69), the NMOS (67) and the NMOS (65), whereas the other NMOS (60) is turned OFF so that the electric current flowing in the PMOS (68), the NMOS (66) and the NMOS (64) is shut off. As a result, the potential of the N11 is brought into a Low state and the output signal VOUT of the inverter (73) becomes close to the level of the Vdd2.
On the other hand, when the input signal VIN is at an L level, one (61) of the input NMOSs is turned OFF so that the electric current flowing in the NMOSs (67) and (65) is shut off, while the other input NMOS (60) is turned ON so that electric current is allowed to flow in the PMOS (68), the NMOSs (66) and (64). Since the PMOS (68) and the PMOS (69) are current mirror connected, the drain voltage of the PMOS (69) enters an unsaturated region while charging the node connected to the N11 and, in consequence, the potential of the N11 becomes close to the level of the Vdd2 so that the output signal of the inverter (73) become close to the level of the Vss2.
The unsaturated region stated herein is a static characteristic of a MOS transistor designated by numeral 56 in FIG. 10, in which the drain to source voltage VDS is low, the drain current ID is low and the changes in ID relative to VDS are significant. Note that numeral 57 in FIG. 10 designates a saturated region.
In the level shift circuit of such a configuration, although a high voltage corresponding to the potential difference between the Vss1 and the Vdd2 is applied only across the gate and drain and across the source and drain of the NMOSs (66) and (67), element breakdown can be avoided because the drains of the NMOSs (66) and (67) have high breakdown voltages. More specifically, even if the level shifting amount of the level shift circuit increases, there is no need to increase the thickness of the gate oxides of the elements and therefore the area occupied by the circuit can be reduced and the operating speed can be increased as compared to the level shift circuit in which high breakdown voltage is ensured by thickening the gate oxides.
In the approach shown in FIG. 12, although high breakdown voltage can be ensured for the elements without increasing the thickness of the gate oxides, the Vdd2 does not operate at lower voltage than the Vdd1 so that low voltage operation cannot be performed. In addition, it has revealed the problem that in a configuration in which operation is performed by charging the input portion of the inverter (73), located in the last stage, with the current source, current consumption increases by increasing the operating speed.